In recent years, with miniaturization and integration of integrated circuits (ICs), a technology of manufacturing a single semiconductor package by stacking a plurality of semiconductor chips using a silicon interposer and a through silicon via (TSV) has been widely studied and developed. Particularly, a process technology of the silicon interposer is recognized as a technology which is absolutely necessary in the field of a 3D IC technology, and continuous research for increasing the degree of integration of a semiconductor device by integrating various passive devices on an interposer is being conducted.
FIG. 1 is a view schematically illustrating a silicon interposer in the related art.
Referring to FIG. 1, the silicon interposer in the related art includes a silicon substrate 101, a first dielectric layer 103, a first metal layer 105 and a second metal layer 107 which are formed at an upper part of the silicon substrate 101, a second dielectric layer 109 for separating the first metal layer 105 from the second metal layer 107 and a via 111 electrically connecting the first metal layer 105 and the second metal layer 107. An inductor is formed by electrically connecting the first metal layer 105, the second metal layer 107 and the via 111.
However, as shown in FIG. 1, the silicon interposer in the related art has a limitation in increasing the degree of integration of a semiconductor package because the inductor is formed only at an upper part of the interposer. In other words, there is a limitation in reducing a thickness of the interposer because the metal layer needs to have more than a predetermined thickness so as to obtain inductance of more than a predetermined value required for a semiconductor package.